Job Reference: ENS190102-ANLYEN : ANALOG LAYOUT ENGINEER (Bangalore, India)
Skill Set: CMOS Analog/Mixed Signal IC Layout
Experience: 3 to 6 years
No. of positions: Multiple
Designing IC Layout of Complex Analog and Mixed Signal Designs like SerDes, PLL, DPLL, Sense Amplifier, Op-Amp, LDO, BIAS. BGR, ADC, Oscillators, Power Management IC’s, GPIO/Special IO’s
ESD and IO Layout Experience is Plus.
Should be Experienced in DMOS, SiGe BCD and CMOS technology in nodes 250nm, 350nm, 180nm 90nm, 45nm 28nm, 16FF, and 7FF is plus
Experienced in Using Industry leading EDA tools like Cadence, Calibre, RedHawk and etc..
Should have experience in automation with Skill, Python and Perl Programming.
Candidate will work on Analog mixed-signal IC Layout with responsibilities ranging from small cell layout design to Big Module IC layout Development like comparators, charge pumps, op-amps, power stages, linear regulators, ADC’s and etc.
Candidate will take a assignment from the Project-Lead/Designer and should understand the requirements and finish the high quality layout in time
Candidate should possess strong DRC/LVS debugging skills.
Knowledge of differnet matching techniques, floor planning, power planning, and signal integrity is a must.
Candidate should possess strong DRC/LVS debugging skills
Personal skills :
Excellent communication and interpersonal skills
Strong and effective presentation skills, able to operate at multiple levels including senior management
EnSilica is a leading IC design house with a consistent record of financial growth and technical excellence since its formation in 2001. Our experienced silicon team are able to deliver a complete digital, RF and mixed-signal ASIC for our customers – from specification through to GDSII tape-out and production silicon.
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