At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Applications Engineer
We're looking for Applications engineer to join our team.
Does this sound like a good role for you?
Synopsys IC Validator (ICV) is a comprehensive signoff DRC / LVS tool architected and proven for In-Design physical verification at leading-edge process nodes. It delivers excellent scalability, superior ease-of-use for the physical designer, and high programmability for easier runset development. The successful candidate would be working on development, qualification and optimization of advanced technology runsets.
With the advent of technology, the PV requirements have become very complex. As a result, the number of checks in runsets have increased multi-fold and warrant fairly challenging coding to meet the foundry requirements. The job requires engineer to develop high quality, high performance runsets, which enable Synopsys customers to validate their advanced technology chips for their manufacturability. Development of a runset involves visualization of hierarchical geometries and coming up with creative solutions to meet the design manual expectations. The quality of the runset is ensured by validating it against a specially designed regression suite whose qualification is a pre-requisite before the runset can be released for production use.
The engineer is also expected to understand any new technology requirements which are currently not supported by the tool and work with R&D and CAE teams to define clear requirements for them. The job also involves handling customer issues which may require debugging runset issues on full chip designs.
Key Qualifications
- B.Tech/M.Tech/MS degree in Electronics/VLSI domain
- Understanding and exposure to transistor CMOS layouts
- A strong understanding of ASIC design flow, VLSI, and/or CAD engineering is desired and knowledge of Perl/Tcl, Unix is a plus
- Experience with Physical Verification EDA tool products like Calibre/Assura/Quartz and product knowledge in any of the areas of like writing foundry decks ( DRC/LVS/ERC/DFM),solving LVS issues, knowledge of foundry processes, understanding of cutting edge DFM requirements are highly desired
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. 
0 to 3 Years 
Salary not disclosed 
Hyderabad
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