Synopsys Inc jobs - Applications Engineer

AE - Emulation

Seeking a highly motivated and innovative verification Engineer with strong theoretical and practical background in validating Simulation/Synthesis/FPGA/Emulation tools/flows. Working as part of a highly experienced emulation team, the candidate will be contributing towards improving the quality of Synopsys Hardware Emulation tool, ZeBu. The position offers the candidate to validate different aspects of the emulation flow by doing directed testing and validating In-house customer designs. Also need to bring up the designs from simulation to emulation flow, interpret and validate the results, and optimize the design until the predetermined functionality along with timing is satisfied. The position offers an excellent opportunity to work with an expert team of emulation engineers responsible for qualifying the zebu backend and runtime tools from specification development to performing functional and performance tests for validating the tool. In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, Xilinx’s ISE, Vivado, ZeBu server,HAPS.

Responsibilities of this job include: The candidate will be responsible for validation of Zebu server’s various compile/runtime flows. The Engineer will need to create test plans, get it reviewed by various stakeholders including the Product validation team, application Engineers, R&D Engineers, both locally and globally, execute the test plan, design and develop tests in VHDL/Verilog/System verilog/C/C++ languages to validate the tool, debugging the issues encountered, reporting the tool issues using CRM, follow up with RD on the fixes, validating the fixes, initiate/participate in meetings with AE’s/R&D’s to discuss on validation progress, quality and sending status reports. Responsible for doing competitive benchmarks and evaluations for full zebu emulation flow. Responsible for analyzing and proposing recommendations to improve the tool, writing block-level testbenches, defining or reviewing verification plans, debugging compile/runtime emulation failures, interacting with customer support.

The successful candidate will have B.Tech / M. Tech and hands-on experience in validating Simulation/Synthesis/FPGA/Emulation tools. Furthermore, candidate must have a deep understanding of Digital Electronics concepts, Verilog/VHDL/System Verilog. Knowledge on areas like Synthesis, simulation, verification, place and route, design reuse and/or physical design is preferred. Proficiency in functional verification using VCS or other simulators and formal verification using Formality or other formal verification tools is preferred. Understanding of FPGA architectures, knowledge and experience on Hardware emulation tool, experience in verification technology, testcase creation, simulation using VCS and other simulators, debugging with Verdi/DVE, familiarity with Unix, scripting languages like perl/bash/c shell/ is a plus along with good organization and communication skills for interacting between different design groups and customer support teams.