Job Reference: ENS170908-ASICDE : ASIC DESIGN ENGINEER/ LEAD (Bangalore, India)
Skill Set: ASIC Design, RTL Coding
Experience: 5 -15 years
No. of positions: Multiple
Background:
- MSEE + minimum 5 years of relevant experience doing digital standard cell based IC design using Verilog, synthesis tools, timing analysis and physical verification tools.
- Experience with mixed signal systems is a must
- Design for testability, scan insertion, scan vector generation
- Familiarity with Cadence and Synopsys design tools
- Debugging ICs and associated evaluation systems in a lab environment
- Experience architecting and implementing DSP functions such as filters and modulators is a plus
- Experience architecting complex devices in deep submicron technologies is a plus
- Experience with UVM and System Verilog is a plus
Personal skills :
- Excellent communication and interpersonal skills
- Strong and effective presentation skills, able to operate at multiple levels including senior management
- Self motivated
- Take ownership of problems
- Creative problem solving
- Team player