Synopsys Inc jobs - ASIC Physical Design Engineer

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

ASIC Physical Design Engineer

Seeking a highly motivated and innovative Physical design engineer with strong theoretical and practical background in Physical design domain.

Job Responsibilities

Requirement is for the Logic library (IP),Solution Group. Work includes PNR view generation, PPA benchmarking activities, Test chip implementation on different tech node logic libraries. Skills focus would be on Place & Route, timing closure, physical verification and design closure.

Job Requirements

• Bachelor or Master degree in electronics or electrical engineering or equivalent from reputed universities with 2-6 years’ experience in ASIC Physical design.
• In depth knowledge of end to end ASIC/SOC flow in submicron process nodes.
• Gate level and circuit level understanding of CMOS logic design.
• Strong Place & Route and Physical verification (DRC/LVS) skills
• Should be familiar with all stages of ASIC design flow including Synthesis, Timing analysis, Floor planning, Power planning, CTS, ECO flow, STA, Power analysis.
• Should be familiar with the Low power concepts & UPF/CPF format
• Good understanding about Technology file, Liberty, Lef, Def, Gds & standard cells view generation process.
• Experience using Synopsys tools like ICC-II, FC, DC, PT, ICV. Also experience on cadence and mentor tools would be advantage
• Good communication, Interpersonal skills, Team player