Description:
• Mtech/Btech in the fields of electronics with 2-5 years of experience with strong focus in Methodology development and flow automation and support in Physical design construction and signoff domains.
• Experience in ASIC Physical Design RTL to GDSII Implementation flow in areas of floor planning, power planning, placement, CTS, routing OR in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality, Timing ECOs, PV/Noise modelling, FEV, Low power
• Multi-voltage scenarios design handling knowledge etc is expected. Any STA closure/convergence execution with Low power design closure is a plus.
• Knowledge of Timing .lib generation, Physical View Generation LEF, NDM etc.
• EDA tool knowledge: ICC2/FusionCompiler/Innovus, PrimeTime/Tempus, Conformal, VCLP…
• Team player, with good problem solving and communication skills.
• Automation skills in PERL and/or TCL and/or Python is an added plus
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