Qusol Consultancy jobs - Design Engineer II

Rtl Front end design engineer RTL frontend design Engineer 4-6 years experience in Verilog/System Verilog RTL design and verification RTL synthesis using Design compiler FPGA Flow using Xilinx DFT knowledge of controlling the clock and reset at the RTL level required Knowledge of MBIST,BSCAN , SCAN would be good Ability to work as a team across the geographical location Knowledge of USB2 and USB3 , Ethernet would be added advantage Knowledge of SPI,I2c,AHB,APB,8051/ARM is preferable Knowledge of UPF is required Requirements This Position is based out in Chennai.