Junior VLSI Engineer
VLSI Freshers: BE/BTech ME/MTech, 70% and above throughout education. 2021, 2022 pass-outs.
Test cases and ensure coverage and Performance goals are achieved for IP and
HDVLS: VERILOG HDL, SV, UVM, C
Strong skills in scripting languages like Perl/ Python / TCL
Work knowledge of RSIC V processor
Development of Verification plans
Front end VLSI development from specification to implementation
The candidate will get to work on one or more aspects of IP development including Specification, Architecting, Design, and Verification across domains.
Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, Test development, etc.
Verification Tasks- System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debugging, regressions using the lasted methodologies such as UVM, Formal verification, etc.
Good problem-solving skills and analytical abilities.
Good team player, interpersonal skills, and communication skills.
High levels of motivation and self-propulsion
Aptitude to pursue a career in the VLSI field.
State Of the art tools and methodologies for IP design including FPGA prototyping
Latest Protocol standards such as AMBA, Ethernet, USB, PCIe, DDR, SD/eMMC, MIPI, DSC
Application space across high-performance mobile computing and communication devices, Servers, etc.
Excellent fundamentals in Digital electronics
Proficiency in structured programming languages such as C, C++, Python
Preferred Exposure to Verilog, VHDL, System Verilog, and VLSI Design/verification methodologies and tools