The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc .
The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc.
At least 2~8+ years’ experience in complex ASIC Design projects.
Have in depth knowledge of entire physical design process from floorplan till GDS generation
Good Exposure to Physical Verification Process
Have hands-on experience in latest sub-micron technologies below 20nm
Hands –on experience in leading PnR tools Synopsys ICC/Cadence Encounter etc
Experience in low power designs and handling congestion or timing critical tiles will be preferred
Should be a quick learner and have good attention to detail
Experience in ECO implementation preferred
Scripting skills in Perl/Python etc
Must have good communication & problem solving skills.
Should be able to handle PnR tasks with minimal supervision
Founded in 1969 as a Silicon Valley start-up, the AMD journey began with dozens of employees focused on leading-edge semiconductor products. From those modest beginnings, AMD has grown into a global company of 10,000 people, achieving many important industry firsts along the way. AMD today develops high-performance computing and visualization products to solve some of the world’s toughest and most interesting challenges. There has never been a better time to be in the semiconductor industry, and we are ready to tackle the next 50 years with high-performance computing and graphics solutions that transform all of our lives.
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