CyientHyderabad jobs - Post Silicon Validation Engineer

Post Silicon Validation Engineer (Cyient)

Job Description Summary(5-7years)

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.

Must-Have:
* 5 years Experience in Performing Post Silicon Validation (PSV) Activities on the Display IPs and/or Media IPs
* Developing Validation test Plans
* Developing any Synthetic & OS Based Content
* Executing Workloads (Synthetic & OS based) on Silicon
* Triaging the failures and Debug to root cause the failure
* Support RTL Level Debug for same failures and suggest changes
* Meet and/or beat client SLAs for IP Debug on Silicon
* Evaluate new team members for technical competencies to build and manage the rest of the PSV Team
* Efficient reporting and Delivery to create a high CSAT

Good to Have:

* Intel Work Flow Experience / Knowledge for RTL / PSV
* Understand client SV Lab set-up, support various systems and lab users
* Ability to work thru late hours (OT) along with the team for critical / RED Flag items/issues, similarly during select weekends on a need basis and as per plan or to catch up on time/schedule slippages