Applications are invited from M.E/M.Tech graduates with specialization in VLSI and BE/BTech in ECE/EEE/ICE for the temporary post of Project Design Engineer in the consultancy project on Algorithmic approach to achieve maximum functional coverage using Constrained Random verification platform. The selected staff would be required to work on developing algorithms for design verification.
1. Post Name: Project Design Engineer
2. The applicants are expected to have a sound knowledge of design verification and exposure to Hardware Description Languages such as Verilog, VHDL and System Verilog. Minimum experience of two years in the relevant field is preferred.
3. Salary: Rs.25,000/= per month (consolidated)
4. Duration of appointment: 3 months (purely on Temporary basis)
5. Contract may be terminated with a minimum one month period of notification
6. Number of Vacancy: 1