Synopsys Inc jobs - RD Engineer

R&D Engineer

Looking for innovative, out of the box thinking IP verification Engineers to be a part of the Hardware Engineering Team under the Hardware Analytics and Test (HAT) Group at Synopsys. Synopsys technology is at the heart of innovations that are changing the way we live and work. The HAT Group is a critical part of the change delivering a complete silicon lifecycle management solution to the customer needs.

The Test & Debug IP verification engineer works on verifying IPs that assist in test, debug, reliability and monitoring of SoCs. The work involves going through hardware development stages like microarchitecture, design, verification and extends to helping customers with SoC integration and Silicon Bring-up of these IPs. The role also involves assisting in IP automation methodologies and flows, to generate, connect and validate the IPs via end to end automation.

Key Qualification

• Ability to come up with a test plan from scratch by studying the IP feature specification.
• Hands on experience in designing and creating verification-IP and/or testbenches for medium sized IPs from scratch.
• Exposure to architecture, design or verification of Debug/DFx/DFT IPs’ design is a strong plus.
• Verification IP Development/Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.
• Knowledge of one or more of protocols: USB/PCI Express/AMBA (AXI, APB, ATB, AHB, ACE).
• Experience in verification methodologies such as UVM/VMM/OVM.
• System Verilog knowledge is a must.
• Hands on experience with simulation tools like VCS/Verdi etc.
• Excellent communication and presentations skills are mandatory. Listening, understanding, and interpreting the customer requirements are a key part of the communications skill set. Good technical problem-solving skills are a must.
  

Qualification

• Bachelors+2 years of relevant experience / Masters +1 years of relevant experience in Electrical Engineering or Computer Engineering or other relevant field of study.
  
  

Preferred Experience

• Experience with creating test plans, verification strategies and testbench architecture.
• Experience with coding testbenches using system Verilog and/or UVM/OVM methodologies.
• Experience with Perl/TCL/Python scripting to create fully automated and one touch regressions systems.
  

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.