Senior Design & Verification (DDR)Engineer-75197
Location: Bangalore, Karnataka, IN
Roles and Responsibilities:
- Verification of complex IPs part of various AMD processor SOCs.
- Understanding architecture and microarchitecture of processor and memory sub systems, DRAM interface protocols like DDR, LPDDR etc
- Test Planning, Implementation and Execution.
- Develop System Verilog (UVM) or C/C++ testbench and verification components.
- Maintain and Interface with existing random generators, models and APIs
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports.
- Debugging regression failures and identify the cause.
Requirements:
- Have in depth knowledge and hands-on experience in complex IP or ASIC or SoC design and functional verification
- Expertise in UVM based verification methodology
- Proficiency in System Verilog, C or C++
- Knowledge of computer architecture, Memory interface protocols like DDR4, DDR5, LPDDR4 is a plus.
- Should be able to work closely with architects, RTL Designers and DV engineers across multiple sites.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Must have good communication & Analytical thinking skills.
- Should be able to provide Technical mentoring and guidance to junior engineers.
Education: Bachelors or Masters with 3-8 years working experience in ASIC / IP / SOC Design Verification