Sr . Engineer / MTS / SMTS
Education
UG
:B.Tech/B.E. in Any Specialization
PG :M.Tech
in Electronics/Telecommunication
Experience
: 2 - 8 years
Location
: Bengaluru, Hyderabad
Job Description
- Responsible
for all aspects of physical design and implementation.
- Responsibilities
include chip floor plan, power / clock distribution, chip assembly and P R,
timing closure, power and noise analysis and back-end verification across
multiple projects.
- High level
of expertise in complete physical implementation tool chain;
- Good working
knowledge and experience of netlist to GDSII flows
- Hands-on
technical experience with deep sub-micron technology ASIC design, STA and
physical implementation
- Expertise in
Synthesis, Static Timing Analysis and Timing Closure of High Performance
Hard-Macros and/or Full Chip Physical Designs
- Should be
independent, self-driven and a strong team player.
- Thorough
understanding and knowledge of the entire Back end flow Netlist to gdsii
- Must be
familiar with Industry standard tools like ICC / Innovus / Encounter
- Should have
expertise in Timing analysis and closure
- Should have
Tcl and perl scripting skills
- Preferred
experience in the latest technology nodes like 7nm/10nm
- Should be
familiar with low-power design and their impact on Back end flow (power
switches / Level shifter / Isolation cell / retention cells)