WIPRO jobs - VLSI Design For Testability - DFT-Vlsi Engineer

VLSI Design For Testability - DFT-Vlsi Engineer

WIPRO
experience 1 to 3 Years
salary Salary not disclosed
qualification
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Posted: 4 Years ago
Views: 6
Applications: 0
Openings: 1

Job Description

VLSI Design For Testability - DFT-Vlsi Engineer

Job Code : 1089179

Location: Bengaluru

Minimum Experience Required: 1-3 YEARS 

Mandatory Skills: VLSI Design For Testability - DFT VLSI Memory BIST and Boundary SCAN, VLSI Design For Testability - DFT, ATPG - VLSI Automatic Test Pattern Generation, Silicon Debug and Characterization, ASIC Synthesis 

Language Skills: English Language

Job Description:
  • Good knowledge of Hierarchical scan synthesis
  • Handle module level scan insertion
  • Handle device scan insertion with multiple clock domains. ATPG
  • Able to do Block/ Device level pattern generation and simulations
  • Scan interleaved with memory BIST patterns gen and validation
  • Device level transition delay testing with multiple clocks, handling exceptions
  • Able to do Sequential ATPG with RAMs and latches, coverage analysis

Job Particulars

Role Engineer
Who can applyExperienced (1 to 3 Years)
Hiring Process Face to Face Interview
Employment TypeFull Time
Job Id191196
StateKarnataka
Country India

About Company

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: Wipro) is a leading global information technology, aconsulting and business process services company. We harness the power of cognitive computing, hyper-automation, robotics, cloud, analytics and emerging technologies to help our clients adapt to the digital world and make them successful. A company recognized globally for its comprehensive portfolio of services, strong commitment to sustainability and good corporate citizenship, we have over 160,000 dedicated employees serving clients across six continents. Together, we discover ideas and connect the dots to build a better and a bold new future.
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