VLSI Design For Testability - DFT-Vlsi Engineer
Job Code : 1089179
Location: Bengaluru
Minimum Experience Required: 1-3 YEARS
Mandatory Skills: VLSI Design For Testability - DFT VLSI Memory BIST and Boundary SCAN, VLSI Design For Testability - DFT, ATPG - VLSI Automatic Test Pattern Generation, Silicon Debug and Characterization, ASIC Synthesis
Language Skills: English Language
Job Description:
- Good knowledge of Hierarchical scan synthesis
- Handle module level scan insertion
- Handle device scan insertion with multiple clock domains. ATPG
- Able to do Block/ Device level pattern generation and simulations
- Scan interleaved with memory BIST patterns gen and validation
- Device level transition delay testing with multiple clocks, handling exceptions
- Able to do Sequential ATPG with RAMs and latches, coverage analysis