Should have SoC and IP level
Functional Verification experience of 2 Yrs.
Expert in VHDL/Verilog/System
Verilog based Test Bench Architecture development. Good hands-on on SV-UVM
based Test environment components implementation should have good ASIC/SOC
System Level Architecture knowledge Proficient in debugging and issue fixing.
Good in communication.
Good Customer Orientation
Minimum Experience Required: 1-3
Mandatory Skills: VLSI HVL Verification Analog Layout, VLSI-Cell Library
Development, Analog and Mixed-signal Verification, Analog Layout Analog
Circuit design, Analog Layout, VLSI HVL
Verification Gate Level Simulation - GLS, VLSI HDL Verification,
VLSI-VERIFICATION PLANNING, VLSI HVL Verification, Hardware Modeling
should possess strong protocol knowledge on PCI-E Gen 2/3/4/5
have hands-on experience on test-case coding, verification planning and debugs.
be independent and able to lead a team of 3 -5 members
Desirable Skills: VLSI-VERIFICATION PLANNING, SOC protocols - AXI and