1 to 3 Years
Posted on 25 Jun 19
Job DescriptionLast Date 24 Aug 19

Job Description

  • Should have SoC and IP level Functional Verification experience of 2 Yrs. 
  • Expert in VHDL/Verilog/System Verilog based Test Bench Architecture development. Good hands-on on SV-UVM based Test environment components implementation should have good ASIC/SOC System Level Architecture knowledge Proficient in debugging and issue fixing.
  • Good in communication.
  • Good Customer Orientation

Roles & Responsibilities:

  • Minimum Experience Required: 1-3 YEARS
  • Mandatory Skills: VLSI HVL Verification Analog Layout, VLSI-Cell Library Development, Analog and Mixed-signal Verification, Analog Layout Analog Circuit design, Analog Layout, VLSI HVL Verification Gate Level Simulation - GLS, VLSI HDL Verification, VLSI-VERIFICATION PLANNING, VLSI HVL Verification, Hardware Modeling  
  • Candidate should possess strong protocol knowledge on PCI-E Gen 2/3/4/5
  • Should have hands-on experience on test-case coding, verification planning and debugs.
  • Should be independent and able to lead a team of 3 -5 members
  • Desirable Skills: VLSI-VERIFICATION PLANNING, SOC protocols - AXI and PCIe

Job Role

Job Type

Interview Type

Face to Face Interview

Company Description
VEE EEE Technologies Solution Private Limited is a Company who are specialized in writing thesis and journal publication for the past 3-4 Years