Smarcon Technologies Private Limited jobs - VLSI Embedded Designer

Having knowledge on the below Synopsis.

Job Description

1. DFT SCAN / ATPG JD: Scan insertions can DRC/Coverage debugATPG Pattern generationGate level simulations ( Zero delays/Timing Delay simulations)Worked on JTAG/P1500 protocolsPerl/Tcl scriptingTiming/Formal verification/PD flow knowledge is plus
2. DFT – MBIST
Looking for verification engineers to do functional verification of DFT components like MBIST, JTAG, BSCAN
Skills
Experience : 3-8 years
Strong knowledge and experience in Scan Insertion, Test compression, ATPG, Memory BIST and JTAG at IC –level for mixed-signal designs.Experience in using Mentor DFT tools, Cadence RC and simulator tools

Define DFT Strategy and Requirement Specification for the designDFT verification for gate-level and timing simulations.

Work cross sites with the design team to define and implement DfT.

Hands-on experience in solving DFT problems, simulation failures, ATPG coverage and DRC improvements.

Support Test engineer in silicon debugs and pattern delivery for ATE

Experience in RTL coding, shell scripting.

Experienced in handling analogue DFT Simulation.
3. PD
Experience:3 – 8 yrs (RTL to GDSII)
Experience and Expertise in Synopsys or Cadence tools like DC-DCTopo, ICC2/Innovus, PTSI, Calibre/ICVProficient in physical design methodology at Block Partition/Top-level Floorplanning, place and route, CTS, Timing and PV signoffProficient in Synthesis methodologies and flows, optimization techniques, area reduction techniquesProficient in low power structures

Excellent in digital design fundamentals

Good debugging skills

Work with Top level team for closing CTS, IO timing.Should have knowledge of low power techniques

Good understanding of physical design flows flow automation and design data management.

Good overall scripting knowledge (Perl, TCL, shell scripts)Good customer support skills across remote sites.Strong communication skills (verbal and written).Teamwork skills and the capability of managing a dynamic work environment.
4. PE 
Experience : 3 - 8 Years
Development of verification plans

Verification environments

Test cases and ensuring coverage and performance goals are achieved for IP and SOC level

Working Knowledge of ARM processors.

HVLS/Tools: SV, UVM, CDomain: Networking, DDR2/3/4, Ethernet PCIe
5. RTL
Experience : 3 - 8 Years
Good understanding of Multi-processor and cache designs 

Hands-on coding experience in Verilog/VHDLFamiliarity with various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols

Has good knowledge of various tools viz Spyglass, 0-in, LEC etc.

Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus.